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s5n 894 4b g.lite adsl transceiver for co and cpe preliminary information (revision 2.1) june 2000 samsung electronics confidential proprietary copyright ? 2000 samsung electronics, inc. all rights reserved
2 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential contents 1. features ................................ ................................ ................................ ............................ 5 2. general description ................................ ................................ ................................ ......... 5 3. logical symbol diagram ................................ ................................ ................................ .. 6 4. pin configuration ................................ ................................ ................................ ............. 7 5. pin description ................................ ................................ ................................ ................. 8 6. functional description ................................ ................................ ................................ ... 11 7. i/o timing description ................................ ................................ ................................ ... 13 8. electrical characteristics ................................ ................................ ............................... 17 9. package description ................................ ................................ ................................ ...... 20
3 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential list of figures figure 1: general block diagram ................................ ................................ ...................... 5 figure 2: logical symbol diagram of the S5N8944B ................................ ......................... 6 figure 3: pin configuration of the S5N8944B ................................ ................................ .... 7 figure 4: functional block diagram of the S5N8944B ................................ ..................... 12 figure 5: afe data i/f timing diagram ................................ ................................ ........... 13 figure 6: afe control i/f timing diagram ................................ ................................ ....... 13 figure 7: motorola read cycle timing diagram ................................ .............................. 14 figure 8: motorola write cycle timing diagram ................................ .............................. 14 figure 9: intel read cycle timing diagram ................................ ................................ ..... 15 figure 10: intel write cycle timing diagram ................................ ................................ ... 15 figure 11: non-atm i/f (byte mode) timing diagram ................................ ..................... 16 figure 12: non-atm i/f (envelope mode) timing diagram ................................ ............. 16 figure 13: atm i/f (utopia-2 transmit) timing diagram ................................ ............... 17 figure 14: atm i/f (utopia-2 receive) timing diagram ................................ ................ 17 figure 15: 160-qfp package diagram ................................ ................................ ............ 20
4 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential list of tables table 1: pin description of the S5N8944B ................................ ................................ ......... 8 table 2: absolute maximum ratings ................................ ................................ ............... 18 table 3: recommended operating conditions ................................ ................................ 18 table 4: power dissipation ................................ ................................ .............................. 18 table 5: dc characteristics ................................ ................................ ............................ 19
5 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 1. features full compliance with itu-t g.lite and g.hs fdm based dmt line coding data rate: up to 3.5 mbps for downstream and 600 kbps for upstream. reach: 5.4 km (18 kft) on 24 awg and 4 km (13.5kft) on 26 awg rate adaptive modem (steps of 32kbps) reed-solomon forward error correction with interleaver frequency and time domain equalizer support fast retraining function support network management function support power management function host interface (intel/motorola) and atm(utopia-2)/non-atm interface 0.25 m m, 2.5v cmos technology operating temperature : -40 c to 85 c package type: 160-qfp 2. general description the S5N8944B is a complete atm-based rate adaptive g.lite adsl modem solution with associated f/w and an analog front-end (s5n8943). the S5N8944B provides all the digital functions such as atm tc, fec codec with interleaver/de-interleaver, adaptive qam codec, fft/ifft, equalizers, digital filters and so on. there are four interfaces for external communications; utopia-2 interface for direct connection to atm systems, serial interface for non-atm applications, 16-bit adc/dac interface, and host interface for general cpus like intel or motorola. the same chipset can be used at both sides of the link, central office and customer premises equipment. the S5N8944B uses 17.664mhz xtal oscillator as a master clock for co side and 17.664mhz vcxo for cpe. figure 1 : general block diagram phone line dmt processor digital interface analog front- end hybrid line driver dsp rom rom atm or non-atm s5n8944 s5n8943 host
6 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 3. logical symbol diagram S5N8944B reset_n ld_tx_pwdn xtal_in ld_rx_pwdn xtal_out ext_clk afe_reset_n pll_flt afe_sdi test_mode afe_sdo test_scn_en afe_sck co_rt afe_sen_n tx_show afe_busy rx_show ntr tx_addr[4:0] dac_ref tx_data[7:0] dac_data[15:0] tx_clk adc_ref tx_enb adc_data[15:0] tx_soc tx_clav tl_tms tl_tck rx_addr[4:0] tl_tdi rx_data[7:0] tl_tdo rx_clk tl_tintp rx_enb tl_bmode[1:0] rx_soc rx_clav hs_sel hs_addr[9:0] hs_data[15:0] hs_cs_n hs_rd_n hs_wr_n hs_ready hs_int hs_wakeup figure 2 : logical symbol diagram of the S5N8944B
7 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 4. pin configuration figure 3 : pin configuration of the S5N8944B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 S5N8944B g.lite adsl transceiver for co and cpe ( 160 -qfp) dac_data_8 dac_data_7 dac_data_6 dac_data_5 dac_data_4 dac_data_3 dac_data_2 vdd7 gnd7 dac_data_1 dac_data_0 dac_ref ext_clk adc_data_0 adc_data_1 adc_data_2 adc_data_3 adc_data_4 adc_data_5 vdd6 gnd6 adc_data_6 adc_data_7 adc_data_8 adc_data_9 adc_data_10 adc_data_11 adc_data_12 adc_data_13 adc_data_14 adc_data_15 vdd5 gnd5 adc_ref afe_sck afe_sen_n afe_sdi afe_sdo test_scn_en tx_data_1 tx_data_0 ntr rx_enb rx_clk rx_soc rx_clav gnd12 vdd12 rx_addr_4 rx_addr_3 rx_addr_2 rx_addr_1 rx_addr_0 rx_data_7 rx_data_6 rx_data_5 rx_data_4 rx_data_3 rx_data_2 gnd13 vdd13 rx_data_1 rx_data_0 gnd14 xtal_out xtal_in vdd14 avdd15 agnd15 agnd16 pll_flt avdd16 agnd17 reset_n tl_bmode_0 tl_bmode_1 test_mode co_rt hs_sel hs_cs_n hs_rd_n hs_wr_n hs_ready vdd1 gnd1 hs_int hs_wakeup hs_data_15 hs_data_14 hs_data_13 hs_data_12 hs_data_11 hs_data_10 gnd2 vdd2 hs_data_9 hs_data_8 hs_data_7 hs_data_6 hs_data_5 hs_data_4 hs_data_3 hs_data_2 gnd3 vdd3 hs_data_1 hs_data_0 hs_addr_9 hs_addr_8 hs_addr_7 hs_addr_6 hs_addr_5 hs_addr_4 gnd4 vdd4 hs_addr_3 hs_addr_2 hs_addr_1 hs_addr_0 tx_data_2 tx_data_3 vdd11 gnd11 tx_data_4 tx_data_5 tx_data_6 tx_data_7 tx_addr_0 tx_addr_1 tx_addr_2 tx_addr_3 tx_addr_4 tx_clav tx_soc tx_clk tx_enb vdd10 gnd10 tl_tintp tl_tdo tl_tdi tl_tck tl_tms vdd9 gnd9 rx_show tx_show ld_rx_pwdn ld_tx_pwdn afe_busy afe_reset_n dac_data_15 dac_data_14 gnd8 vdd8 dac_data_13 dac_data_12 dac_data_11 dac_data_10
8 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 5. pin description table 1 : pin description of the S5N8944B no name i/o description 155 reset_n i system master reset (active low) 147 xtal_in i 146 xtal_out o system master clock (17.664mhz xtal oscillator for co, vcxo for cpe) 67 ext_clk i external clock for test (not used in normal mode, pull-down) 152 pll_flt o pll pump out 158 test_mode i [0] normal mode, [1] test mode 41 test_scn_en i scan enable (set to ? 0 ? in normal mode) 159 co_rt i [0] co, [1] cpe 93 tx_show o tx showtime (active high. connect to led) 94 rx_show o rx showtime (active high. connect to led) 123 ntr i/o atm network timing reference (8khz) (i: co_rt=1, o: co_rt=0) 108 tx_addr_4 109 tx_addr_3 110 tx_addr_2 111 tx_addr_1 112 tx_addr_0 i utopia tx address [4:0] 113 tx_data_7 114 tx_data_6 115 tx_data_5 116 tx_data_4 119 tx_data_3 120 tx_data_2 121 tx_data_1 122 tx_data_0 i utopia tx data [7:0] 105 tx_clk i utopia tx clock (25mhz) 104 tx_enb i utopia tx enable 106 tx_soc i utopia tx start of cell 107 tx_clav oz utopia tx cell available 130 rx_addr_4 131 rx_addr_3 132 rx_addr_2 133 rx_addr_1 134 rx_addr_0 i utopia rx address [4:0] 135 rx_data_7 136 rx_data_6 137 rx_data_5 138 rx_data_4 139 rx_data_3 oz utopia rx data [7:0]
9 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 140 rx_data_2 143 rx_data_1 144 rx_data_0 125 rx_clk i utopia rx clock (25mhz) 124 rx_enb i utopia rx enable 126 rx_soc oz utopia rx start of cell 127 rx_clav oz utopia rx cell available 160 hs_sel i host interface type selection [0] motorola, [1] intel 29 hs_addr_9 30 hs_addr_8 31 hs_addr_7 32 hs_addr_6 33 hs_addr_5 34 hs_addr_4 37 hs_addr_3 38 hs_addr_2 39 hs_addr_1 40 hs_addr_0 i host address [9:0] 9 hs_data_15 10 hs_data_14 11 hs_data_13 12 hs_data_12 13 hs_data_11 14 hs_data_10 17 hs_data_9 18 hs_data_8 19 hs_data_7 20 hs_data_6 21 hs_data_5 22 hs_data_4 23 hs_data_3 24 hs_data_2 27 hs_data_1 28 hs_data_0 b host data [15:0] 1 hs_cs_n i host chip select (active low) 2 hs_rd_n i motorola : not used intel : host read enable (active low) 3 hs_wr_n i motorola : [0] write enable, [1] read enable intel : write enable (active low) 4 hs_ready oz motorola : dtack (active low) intel : ready (active high) 7 hs_int o motorola : irq (active low) intel : int (active high) 8 hs_wakeup oz host wakeup [0] active, [hi-z] disable 91 ld_tx_pwdn o tx line driver power-down (active high) 92 ld_rx_pwdn o rx line driver power-down (active high)
10 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 89 afe_reset_n o afe reset (active low) 43 afe_sdi i afe serial input data (pull-up) 42 afe_sdo o afe serial output data 45 afe_sck o afe serial clock 44 afe_sen_n o afe serial enable (active low) 90 afe_busy i afe serial busy (active high, pull-down) 68 dac_ref o dac data reference (4.416mhz) 88 dac_data_15 87 dac_data_ 14 84 dac_data_ 13 83 dac_data_ 12 82 dac_data_ 11 81 dac_data_ 10 80 dac_data_ 9 79 dac_data_ 8 78 dac_data_ 7 77 dac_data_ 6 76 dac_data_ 5 75 dac_data_ 4 74 dac_data_ 3 73 dac_data_ 2 70 dac_data_ 1 69 dac_data_ 0 o dac data [15:0] 46 adc_ref i not used in normal mode (pull-down) 49 adc_data _15 50 adc_data_ 14 51 adc_data_ 13 52 adc_data_ 12 53 adc_data_ 11 54 adc_data_ 10 55 adc_data_ 9 56 adc_data_ 8 57 adc_data_ 7 58 adc_data_ 6 61 adc_data_ 5 62 adc_data_ 4 63 adc_data_ 3 64 adc_data_ 2 65 adc_data_ 1 66 adc_data_ 0 i adc data [15:0] 97 tl_tms i teaklite jtag test mode selection 98 tl_tck i teaklite jtag test clock 99 tl_tdi i teaklite jtag test data in 100 tl_tdo oz teaklite jtag test data out 101 tl_tintp o teaklite tjam interrupt to host 157 tl_bmode _1 i teaklite boot mode selection [0] reset, [1] boot from host [2] boot from jtag, [3] self-booting
11 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 156 tl_bmode _0 5 vdd1 26 vdd3 48 vdd5 60 vdd6 85 vdd8 103 vdd10 118 vdd11 142 vdd13 p1 2.5v supply voltage 149 avdd15 153 avdd16 p1 2.5v analog supply voltage 16 vdd2 36 vdd4 72 vdd7 96 vdd9 129 vdd12 148 vdd14 p1 3.3v supply voltage 6 gnd1 15 gnd2 25 gnd3 35 gnd4 47 gnd5 59 gnd6 71 gnd7 86 gnd8 95 gnd9 102 gnd10 117 gnd11 128 gnd12 141 gnd13 145 gnd14 p0 digital ground 150 agnd15 151 agnd16 154 agnd17 p0 analog ground i = input o = output oz = tri-state output b = bi-direction p 1 = power p0 = ground 6. functional description the g.lite adsl modem consists of two main chip s; adsl transceiver chip (s5n8944) and analog front-end chip (s5n8943). the analog front-end provide s an analog interface with line
12 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential drivers and hybrid components to connect the pstn. the adsl transceiver provides all the digital functions as depicted in figure 4 . the input bit stream is divided into bit slices and they are fed into the qam which are allocated to 128 subchannels according to the bit loading table. the bit slices are then converted to frequency-domain complex samples by the qam encoders. the 256 complex samples are changed to 256 time-domain samples by ifft. the tx filter performs band separation and interpolation functions. the received signals are attenuated and distorted in terms of both phase and amplitude. pll fixes the phase errors within 4 samples using the 276khz pilot tone transmitted from the co side. the ones over 4 samples are fixed by the sync recovery algorithm using a known synchronization symbol. the teq is a filter that adaptively alters the channel so that the impulse response is reduced to the length of the cyclic prefix which will be removed prior to fft. the feq is a one tap complex adaptive filter for each subchannel, which adjusts the gains and phases of the received signals. the equalizers are adaptively updated due to the transmission channel environment. in fdm-based dmt (discrete multitone) modulation , the frequency band, 0 to 552khz, is divided into 128 equi-spaced subchannels, of which 26khz (#6) to 134khz (#31) is allocated for the upstream, and 142khz (#33) to 548khz (#127) for the downstream. the nyquist rate, therefore, should be 1.104mhz ( 276khz ) . dmt inherently transmits an optimized time-variable spectrum. this spectrum is adjusted according to the desired data rate and the transmission characteristics (transfer function and noise spectrum) on each and every subchannel. for this, co and cpe transmit 128 4khz-wide tone downstream and upstream respectively to each other during initialization. they measure the quality of each of these received tones and then decide whether a tone has sufficient quality to be used for further transmission and, if so, how much data this tone should carry relative to the other tones that are used. they inform the bit loading result to each other. figure 4 : functional block diagram of the S5N8944B atm framer atm or non-atm host fec codec qam codec feq teq ifft 256/64 tx filter fft 256/64 rx filter dsp dac adc
13 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 7. i/o timing description dac_ref (4.416mhz) dac_dat[15:0] (4.416mhz) adc_dat[15:0] (2.208mhz) parameter description min max unit t 1 adc_dat setup to dac_ref 30 ns t 2 adc_dat hold after dac_ref 1 ns t 3 dac_dat setup to dac_ref - 15 ns t 4 dac_dat hold after dac_ref - 15 ns figure 5 : afe data i/f timing diagram afe_sen_n afe_scl (1.104mhz) afe_sdo afe_sdi afe_busy parameter description min max unit t 1 afe_sdi setup to afe_scl - 30 ns t 2 afe_sen_n before afe_scl - 30 ns t 3 afe_sen_n - from afe_scl - 15 ns figure 6 : afe control i/f timing diagram t 1 t 2 cs1 cs0 a4 a0 rw d15 d14 d0 d15 d14 d0 t 1 t 3 t 2 t 3 t 4
14 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential hs_addr[9 :0] hs_data[15:0] hs_cs_n hs_wr_n hs_ready (dtackn) parameter description min max unit t 1 hs_addr setup to hs_cs_n 0 ns t 2 hs_wr_n - before hs_cs_n 0 ns t 3 hs_data valid from hs_ready 10 ns t 4 hs_ready hi-z from hs_cs_n - 1 5 ns t 5 hs_data hold after hs_cs_n - 5 ns figure 7 : motorola read cycle timing diagram hs_addr[9 :0] hs_data[15:0] hs_cs_n hs_wr_n hs_ready (dtackn) parameter description min max unit t 1 hs_addr setup to hs_cs_n 0 ns t 2 hs_wr_n before hs_cs_n 0 ns t 3 hs_data valid from hs_cs_n 50 ns t 4 hs_ready hi-z from hs_cs_n - 1 5 ns t 5 hs_data hold after hs_cs_n - 5 ns figure 8 : motorola write cycle timing diagram t 4 t 5 t 2 t 5 t 3 valid t 1 t 2 t 4 valid t 1 t 3
15 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential hs_addr[9 :0] hs_data[15:0] hs_cs_n hs_rd_n hs_ready parameter description min max unit t 1 hs_addr setup to hs_cs_n 0 ns t 2 hs_cs_n before hs_rd_n 0 ns t 3 hs_data valid from hs_rd_n 170 ns t 4 hs_cs_n - from hs_rd_n - 0 ns t 5 hs_ready from hs_rd_n 0 20 ns t 6 hs_data hold after hs_rd_n - 5 ns figure 9 : intel read cycle timing diagram hs_addr[9 :0] hs_data[15:0] hs_cs_n hs_wr_n hs_ready parameter description min max unit t 1 hs_addr setup to hs_cs_n 0 ns t 2 hs_cs_n before hs_wr_n 0 ns t 3 hs_data valid from hs_wr_n 50 ns t 4 hs_cs_n - from hs_wr_n - 0 ns t 5 hs_ready from hs_wr_n 0 20 ns t 6 hs_data hold after hs_wr_n - 5 ns figure 10 : intel write cycle timing diagram t 2 t 3 t 4 t 2 valid t 1 t 3 t 6 valid t 1 t 6 t 4 t 5 t 5
16 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential rx_data_3 (tx_scl) rx_data_4 (tx_sdav) rx_addr_0 (tx_sda) (lsb) rx_data_1 (rx_scl) rx_data_2 (rx_sdav) rx_data_0 (rx_sda) (lsb) parameter description min max unit t 1 tx_scl frequency 1 25 mhz figure 11 : non-atm i/f (byte mode) timing diagram rx_data_3 (tx_scl) rx_data_4 (tx_sdav) rx_addr_0 (tx_sda) (lsb) rx_data_1 (rx_scl) rx_data_2 (rx_sdav) rx_data_0 (rx_sda) (lsb) parameter description min max unit t 1 rx_scl frequency 1 25 mhz figure 12 : non-atm i/f (envelope mode) timing diagram t 1 d7 d1 d2 d3 d4 d5 d6 d0 d7 d1 d2 d3 d4 d5 d6 d7 d1 d2 d3 d4 d5 d6 d0 d7 d1 d2 d3 d4 d5 d6 d0 d0 t 1
17 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential tx_clk (25mhz) tx_addr[4:0] tx_clav tx_enb tx_data[7:0] tx_soc (atm0) (atm1) parameter description min max unit t 1 signal hold after tx_clk - 5 10 ns figure 13 : atm i/f (utopia-2 transmit) timing diagram rx_clk (25mhz) rx_addr[4:0] rx_clav rx_enb rx_data[7:0] rx_soc (atm0) (atm1) parameter description min max unit t 1 signal hold after rx_clk - 5 10 ns figure 14 : atm i/f (utopia-2 receive) timing diagram 8. electrical characteristics h1 h2 p48 p47 p46 00 1f 1f 1f 1f 01 02 03 h3 t 1 h1 h2 p48 p47 p46 00 1f 1f 1f 1f 01 02 03 p45 t 1
18 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential table 2 : absolute maximum ratings symbol parameter rating unit v dd dc supply voltage 3.6 2.5v input buffer 3.6 3.3v input buffer 4.6 v in dc input voltage 5v-tolerant input buffer 6.5 2.5v buffer 3.6 v out dc output voltage 3.3v buffer 4.6 v i latch latch-up current 200 ma t stg storage temperature -65 to 150 c table 3 : recommended operating conditions symbol parameter rating unit 2.5v i/o 2.3 to 2.7 3.3v i/o 3.0 to 3.6 dc supply voltage 5v-tolerant i/o 3.0 to 3.6 v dd analog core dc supply voltage 2.5v core 2.5 5% v t a operating temperature (ambient) industrial -40 to 85 c table 4 : power dissipation symbol parameter min typ max unit p d power dissipation - 0.35 0.4 w
19 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential table 5 : dc characteristics symbol parameters min typ max unit v ih input high voltage 1.7(0.7v dd ) - - v il input low voltage - - 0.7(0.3v dd ) v oh output high voltage 1.9(2.4) - - v ol output low voltage - - 0.5(0.4) vt switching threshold - 0.5v dd - vt + schmitt trigger, positive-going threshold - - 1.9(2.0) vt- schmitt trigger, negative-going threshold 0.6(0.8) - - v h schmitt trigger , vt + - vt- 0.5 0.65(0.575) 0.8(0.65) v -10 - 10 i ih input high current (v in =v dd ) 10* 25(33)* 50(60)* -10 - 10 i il input low current (v in =v ss ) -50(-60)* -25(-33)* -10* i oz tri-state output leakage current -10 - 10 i os output short circuit current -55 - 55 i dd quiescent supply current - - 100 m a c in input capacitance - - 4 c out output capacitance - - 4 pf notes: 1. () ? in case of 5v-tolerant 2. * - input buffer with pull-up or pull-down. 3. c in and c out exclude package parastics.
20 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential 9. package description figure 15 : 160-qfp package diagram #1 #160 a: 31.20 0.25 b: 28.00 0.10 b a a b (1.325) 0.30 0.08 m 0.12 0.65bsc 0.25min 3.40 0.25 4.07max 0.10 0.73~1.03 0~7
21 S5N8944B g.lite adsl transceiver for co and cpe preliminary information (rev.2.1 ) confidential revision history revision no. date description 1.0 2000-02-01 ks8944a (rev.1) released. 2.0 2000-06-15 S5N8944B (rev.2) released. - internal memories reduced. - input pin, noise_det (41) changed to test_scn_en . - output pin, gp_out_1 (93) changed to tx_show . - output pin, gp_out_0 (94) changed to rx_show . - tc byte alignment problem fixed. - tx_data latched at the rising edge of tx_clk. 2.1 2000-06-22 160-qfp package description added. pin description modified. important notice the information furnished by samsung electronics in this document is belived to be accurate and reliable. however, no resposibility is assumed by samsung electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of samsung electronics. samsung electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. for more information tel: (82)-(31)-209-8301, fax: (82)-(31)-209-8309 e-mail: kimil@sec.samsung.com http://www.intl.samsungsemi.com copyright ? 2000 samsung electronics, inc. all rights reserved

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